URL https://opencores.org/ocsvn/spimaster/spimaster/trunk

Subversion Repositories spimaster

[/] [spimaster/] [trunk/] [Aldec/] [design0/] - Rev 2

Path
/trunk/Aldec
/trunk/Aldec/design0
/trunk/Aldec/design0/design0.adf
/trunk/Aldec/design0/fsm.set
/trunk/Aldec/design0/src
/trunk/Aldec/design0/src/initSD.asf
/trunk/Aldec/design0/src/readWriteSDBlock.asf
/trunk/Aldec/design0/src/readWriteSPIWireData.asf
/trunk/Aldec/design0/src/sendCmd.asf
/trunk/Aldec/design0/src/spiCtrl.asf
/trunk/bench
/trunk/bench/testCase0.v
/trunk/bench/testHarness.v
/trunk/doc
/trunk/doc/spiMaster_FSM.pdf
/trunk/doc/spiMaster_Specification.pdf
/trunk/doc/src
/trunk/doc/src/spiMaster_Specification.sxw
/trunk/model
/trunk/model/sdModel.v
/trunk/model/wb_master_model.v
/trunk/RTL
/trunk/RTL/ctrlStsRegBI.v
/trunk/RTL/initSD.v
/trunk/RTL/readWriteSDBlock.v
/trunk/RTL/readWriteSPIWireData.v
/trunk/RTL/sendCmd.v
/trunk/RTL/sm_dpMem_dc.v
/trunk/RTL/sm_fifoRTL.v
/trunk/RTL/sm_RxFifo.v
/trunk/RTL/sm_RxFifoBI.v
/trunk/RTL/sm_TxFifo.v
/trunk/RTL/sm_TxFifoBI.v
/trunk/RTL/spiCtrl.v
/trunk/RTL/spiMaster.v
/trunk/RTL/spiMasterWishBoneBI.v
/trunk/RTL/spiMaster_defines.v
/trunk/RTL/spiTxRxData.v
/trunk/RTL/timescale.v
/trunk/sim
/trunk/sim/build_icarus.bat
/trunk/sim/compile.do
/trunk/sim/filelist.icarus
/trunk/sim/modelsim.ini
/trunk/sim/run.do
/trunk/sim/run_icarus.bat
/trunk/sim/wave.do
/trunk/syn
/trunk/syn/spiMaster.qpf
/trunk/syn/spiMaster.qsf