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[/] [t48/] [tags/] [rel_0_5_beta/] [rtl/] - Rev 143
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Last modification
- Rev 143, 2004-10-25 19:39:24 GMT
- Author: arniml
- Log message:
- Fix bug report:
"RD' and WR' not asserted for INS A, BUS and OUTL BUS, A"
rd is asserted for INS A, BUS
wr is asserted for OUTL BUS, A
P1, P2 and BUS are written in first instruction cycle
