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https://opencores.org/ocsvn/t48/t48/trunk
Subversion Repositories t48
[/] [t48/] [tags/] [rel_1_0/] [rtl/] [vhdl/] - Rev 172
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Last modification
- Rev 172, 2005-05-10 22:36:23 GMT
- Author: arniml
- Log message:
- save data from wishbone bus in register bank with wb_ack
necessary to hold data from peripheral/memory until it is read by T48