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[/] [test_project/] [trunk/] [rtl/] [verilog/] [components/] [or1k_top/] - Rev 42

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Last modification

  • Rev 42, 2009-05-06 19:45:47 GMT
  • Author: julius
  • Log message:
    Fixed up to allow compilation with verilator. Mostly separation of modules into appropriate file names. However some vector declaration changes in the smii module has definitely broken it.

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