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[/] [test_project/] [trunk/] [rtl/] [verilog/] [components/] [ram_wb/] - Rev 88
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Last modification
- Rev 45, 2009-05-13 18:44:55 GMT
- Author: julius
- Log message:
- Many updates including internal SRAM instead of SDRAM as default, so inclusion of the SRAM model, a new VMEM generation program, and script and testbench updates to allow the switching on and off for SDRAM, which as mentioned is now off by default
