Subversion Repositories ts7300_opencore

Last modification

• Rev 2, 2006-06-13 00:53:36 GMT
• Author: joff

• Log message:

  Initial import of ts7300_opencore. Quartus II project tree for
  Technologic Systems TS-7300 FPGA Linux Computer. Contains WISHBONE
  bridge verilog as well as pin locks, timing constraints, and various
  other Quartus II project metadata. Also included is a sample
  implementation of the open-ethernet core as well as a stub WISHBONE slave
  demonstrating a 32-bit register in the address space of the ARM9 CPU running
  Linux.