URL
https://opencores.org/ocsvn/uart16550/uart16550/trunk
Subversion Repositories uart16550
[/] [uart16550/] [tags/] [rel_2/] [sim/] - Rev 95
Directory listing | View Log | Compare with Previous | RSS feed
Last modification
- Rev 95, 2004-03-27 04:07:47 GMT
- Author: tadejm
- Log message:
- Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead only when TX FIFO is empty. This causes testcases not to finish.