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https://opencores.org/ocsvn/uart16550/uart16550/trunk
Subversion Repositories uart16550
[/] [uart16550/] [trunk/] [rtl/] [verilog/] - Rev 101
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Last modification
- Rev 101, 2004-05-21 12:35:15 GMT
- Author: tadejm
- Log message:
- Added 2 LSB address generation dependent on select lines and LITLE/BIG endian when UART is in 32-bit mode.