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https://opencores.org/ocsvn/uart16550/uart16550/trunk
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[/] [uart16550/] [trunk/] [rtl/] [verilog/] - Rev 98
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Last modification
- Rev 98, 2004-05-21 11:43:25 GMT
- Author: tadejm
- Log message:
- Added to synchronize RX input to Wishbone clock.