URL https://opencores.org/ocsvn/uart2bus/uart2bus/trunk

Subversion Repositories uart2bus

[/] [uart2bus/] [trunk/] [verilog/] [bench/] - Rev 14

Rev 12, 2012-02-25 10:48:40 GMT
Author: motilito
Log message:
Updated Verilog implementation to sync with VHDL to include internal bus request/grant mechanism.

Path
/uart2bus/trunk/doc/UART to Bus Core Specifications.pdf
/uart2bus/trunk/verilog/bench/tb_bin_uart2bus_top.v
/uart2bus/trunk/verilog/bench/tb_txt_uart2bus_top.v
/uart2bus/trunk/verilog/bench/tb_uart2bus_top.v
/uart2bus/trunk/verilog/bench/uart_tasks.v
/uart2bus/trunk/verilog/rtl/uart2bus_top.v
/uart2bus/trunk/verilog/rtl/uart_parser.v