URL https://opencores.org/ocsvn/uart2bus/uart2bus/trunk

Subversion Repositories uart2bus

[/] [uart2bus/] [trunk/] [verilog/] [bench/] - Rev 4

Rev 4, 2010-04-02 19:54:36 GMT
Author: motilito
Log message:
Corrected some problems in the binary mode protocol test bench.
Updated documentation.

Path
/uart2bus/trunk/doc/UART to Bus Core Specifications.pdf
/uart2bus/trunk/verilog/bench/readme.txt
/uart2bus/trunk/verilog/bench/tb_bin_uart2bus_top.v
/uart2bus/trunk/verilog/bench/tb_txt_uart2bus_top.v
/uart2bus/trunk/verilog/bench/Test Bench Binary Mode - tb_uart2bus_top.v
/uart2bus/trunk/verilog/bench/Test Bench Text Mode - tb_uart2bus_top.v
/uart2bus/trunk/verilog/rtl/uart2bus_top.v
/uart2bus/trunk/verilog/sim/icarus/block.cfg
/uart2bus/trunk/verilog/sim/icarus/block_bin.cfg
/uart2bus/trunk/verilog/sim/icarus/block_txt.cfg
/uart2bus/trunk/verilog/sim/icarus/compile.bat
/uart2bus/trunk/verilog/sim/icarus/compile_bin.bat
/uart2bus/trunk/verilog/sim/icarus/compile_txt.bat