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https://opencores.org/ocsvn/uart_fifo_cpu_if_sv_testbench/uart_fifo_cpu_if_sv_testbench/trunk
Subversion Repositories uart_fifo_cpu_if_sv_testbench
[/] [uart_fifo_cpu_if_sv_testbench/] [trunk/] [bench/] - Rev 2
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Last modification
- Rev 2, 2011-01-03 10:06:00 GMT
- Author: andrewbridger
- Log message:
- Added complete UART RTL and testbench. Both compile, but not debugged in simulator yet. Synchronous FIFO yet to be added. File headers need tidying.