URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [bench/] - Rev 13

Rev 13, 2009-11-06 09:11:58 GMT
Author: mikaeljf
Log message:
Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback.

Path
/versatile_mem_ctrl/trunk/bench/tb.v
/versatile_mem_ctrl/trunk/rtl/verilog/burst_length_counter_defines.v
/versatile_mem_ctrl/trunk/rtl/verilog/ddr_16.fzm
/versatile_mem_ctrl/trunk/rtl/verilog/ddr_16_defines.v
/versatile_mem_ctrl/trunk/rtl/verilog/latency_counter_defines.v
/versatile_mem_ctrl/trunk/rtl/verilog/Makefile
/versatile_mem_ctrl/trunk/rtl/verilog/pre_delay_counter_defines.v
/versatile_mem_ctrl/trunk/rtl/verilog/ref_delay_counter_defines.v
/versatile_mem_ctrl/trunk/rtl/verilog/versatile_mem_ctrl_ip.v
/versatile_mem_ctrl/trunk/rtl/verilog/versatile_mem_ctrl_top.v
/versatile_mem_ctrl/trunk/syn
/versatile_mem_ctrl/trunk/syn/xilinx
/versatile_mem_ctrl/trunk/syn/xilinx/bin
/versatile_mem_ctrl/trunk/syn/xilinx/bin/versatile_mem_ctrl.ucf
/versatile_mem_ctrl/trunk/syn/xilinx/run