URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [rtl/] - Rev 22

Rev 22, 2010-02-21 20:07:01 GMT
Author: mikaeljf
Log message:
Updated the Altera timing constraints file, also minor updates of defines file and Makefile.

Path
/versatile_mem_ctrl/trunk/rtl/verilog/ddr_16_defines.v
/versatile_mem_ctrl/trunk/rtl/verilog/Makefile
/versatile_mem_ctrl/trunk/rtl/verilog/versatile_mem_ctrl_ip.v
/versatile_mem_ctrl/trunk/syn/altera/bin/versatile_memory_controller.sdc