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[/] [versatile_mem_ctrl/] [trunk/] [syn/] - Rev 15

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Last modification

  • Rev 15, 2010-02-04 14:21:43 GMT
  • Author: mikaeljf
  • Log message:
    Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera.

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