URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [syn/] [altera/] [run/] - Rev 113

Rev 15, 2010-02-04 14:21:43 GMT
Author: mikaeljf
Log message:
Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera.

Path
/versatile_mem_ctrl/trunk/bench/tb.v
/versatile_mem_ctrl/trunk/bench/tb_defines.v
/versatile_mem_ctrl/trunk/bench/wb0_ddr.fzm
/versatile_mem_ctrl/trunk/bench/wb1_ddr.fzm
/versatile_mem_ctrl/trunk/bench/wb4_ddr.fzm
/versatile_mem_ctrl/trunk/rtl/verilog/dcm_pll.v
/versatile_mem_ctrl/trunk/rtl/verilog/ddr_16.fzm
/versatile_mem_ctrl/trunk/rtl/verilog/ddr_16_defines.v
/versatile_mem_ctrl/trunk/rtl/verilog/ddr_ff.v
/versatile_mem_ctrl/trunk/rtl/verilog/delay.v
/versatile_mem_ctrl/trunk/rtl/verilog/Makefile
/versatile_mem_ctrl/trunk/rtl/verilog/pre_delay_counter_defines.v
/versatile_mem_ctrl/trunk/rtl/verilog/versatile_mem_ctrl_defines.v
/versatile_mem_ctrl/trunk/rtl/verilog/versatile_mem_ctrl_ip.v
/versatile_mem_ctrl/trunk/rtl/verilog/versatile_mem_ctrl_top.v
/versatile_mem_ctrl/trunk/sim
/versatile_mem_ctrl/trunk/sim/rtl_sim
/versatile_mem_ctrl/trunk/sim/rtl_sim/bin
/versatile_mem_ctrl/trunk/sim/rtl_sim/bin/sim_altera.tcl
/versatile_mem_ctrl/trunk/sim/rtl_sim/bin/sim_xilinx.tcl
/versatile_mem_ctrl/trunk/sim/rtl_sim/run
/versatile_mem_ctrl/trunk/syn/altera
/versatile_mem_ctrl/trunk/syn/altera/bin
/versatile_mem_ctrl/trunk/syn/altera/bin/versatile_memory_controller.sdc
/versatile_mem_ctrl/trunk/syn/altera/bin/versatile_memory_controller.tcl
/versatile_mem_ctrl/trunk/syn/altera/run
/versatile_mem_ctrl/trunk/syn/xilinx/bin/versatile_memory_controller.ucf
/versatile_mem_ctrl/trunk/syn/xilinx/bin/versatile_mem_ctrl.ucf