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[/] [vga_lcd/] [tags/] [rel_1/] [rtl/] [verilog/] - Rev 39
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Last modification
- Rev 39, 2002-04-20 10:02:39 GMT
- Author: rherveille
- Log message:
- Changed video timing generator.
Changed wishbone master vertical gate count code.
Fixed a potential bug in the wishbone slave (cursor color register readout).