URL https://opencores.org/ocsvn/wbddr3/wbddr3/trunk

Subversion Repositories wbddr3

[/] [wbddr3/] [trunk/] [bench/] [cpp/] - Rev 12

Rev 12, 2016-08-01 21:44:03 GMT
Author: dgisselq
Log message:
Added the write-read and write-precharge extra delays into both module and
simulation.

Path
/wbddr3/trunk/bench/cpp/ddrsdramsim.cpp
/wbddr3/trunk/bench/cpp/ddrsdramsim.h
/wbddr3/trunk/bench/cpp/ddrsdram_tb.cpp
/wbddr3/trunk/rtl/wbddrsdram.v