URL https://opencores.org/ocsvn/wbddr3/wbddr3/trunk

Subversion Repositories wbddr3

[/] [wbddr3/] [trunk/] [bench/] [cpp/] - Rev 6

Rev 6, 2016-07-30 01:49:36 GMT
Author: dgisselq
Log message:
Lots of bug fixes. The controller now proceeds through the proper reset
logic into the first write. This includes activating the needed bank and the
next one, and then issuing the write command. It doesn't complete the write
command yet, but that's the next step.

Path
/wbddr3/trunk/bench/cpp/ddrsdramsim.cpp
/wbddr3/trunk/bench/cpp/ddrsdramsim.h
/wbddr3/trunk/bench/cpp/ddrsdram_tb.cpp
/wbddr3/trunk/rtl/wbddrsdram.v