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[/] [xulalx25soc/] [trunk/] [rtl/] [cpu/] - Rev 31

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Last modification

  • Rev 31, 2016-03-10 23:01:08 GMT
  • Author: dgisselq
  • Log message:
    A bug fix, although one that rearranges the bus. The first four I/O locations
    have been adjusted. The new locations are reflected in wishbone.html. In
    addition, the PWM and UART devices no longer create bus errors when accessed.
    Finally, this version uses a `define XULA25 to determine whether or not to build
    for the XuLA2-LX9 or the XuLA2-LX25. If defined, it will build for the
    XuLA2-LX25. If not, for the XuLA2-LX9. The ideal location for this define
    would be to place it into your Xilinx configuration, should you wish to build
    for the LX25.

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