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[/] [yifive/] - Rev 11

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Last modification

  • Rev 11, 2021-06-07 15:59:05 GMT
  • Author: dinesha
  • Log message:
    syntacore directory update
Path
/yifive/trunk/caravel_yifive/verilog/rtl/lib/sync_fifo.sv
/yifive/trunk/caravel_yifive/verilog/rtl/lib/wb_interface.v
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/docs
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/docs/img
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/docs/img/scr1_cluster.svg
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/docs/scr1_eas.pdf
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/docs/scr1_um.pdf
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/LICENSE
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/Makefile
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/README.md
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/ahb_top.files
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/axi_top.files
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core.files
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/pipeline
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_ipic.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_csr.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_exu.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_hdu.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_idu.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ifu.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_lsu.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_tdu.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_tracelog.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/primitives
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/primitives/scr1_cg.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/primitives/scr1_reset_cells.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/scr1_clk_ctrl.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/scr1_core_top.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/scr1_dm.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/scr1_dmi.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/scr1_scu.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/scr1_tapc.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/scr1_tapc_shift_reg.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/scr1_tapc_synchronizer.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/includes
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/includes/scr1_ahb.svh
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_description.svh
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_types.svh
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/includes/scr1_csr.svh
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/includes/scr1_dm.svh
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/includes/scr1_hdu.svh
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/includes/scr1_ipic.svh
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/includes/scr1_memif.svh
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/includes/scr1_riscv_isa_decoding.svh
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/includes/scr1_scu.svh
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/includes/scr1_search_ms1.svh
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/includes/scr1_tapc.svh
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/includes/scr1_tdu.svh
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/includes/scr1_wb.svh
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/run_modemsim
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_ahb.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_router.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_wb.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_dp_memory.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_imem_ahb.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_imem_router.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_imem_wb.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_mem_axi.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_tcm.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_timer.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_top_ahb.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_top_axi.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/wb_top.files
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/synth
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/synth/Makefile
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/synth/run_synth
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/synth/synth.tcl

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