URL https://opencores.org/ocsvn/10_100m_ethernet-fifo_convertor/10_100m_ethernet-fifo_convertor/trunk

Subversion Repositories 10_100m_ethernet-fifo_convertor

[/] [10_100m_ethernet-fifo_convertor/] - Rev 7

Rev 7, 2009-10-10 10:02:58 GMT
Author: antiquity
Log message:
Add the test file test_feedback, and add a variable to eliminate the delay between Tx and Rx

Path
/10_100m_ethernet-fifo_convertor/trunk/rtl/verilog/common.v
/10_100m_ethernet-fifo_convertor/trunk/rtl/verilog/RxModule.v
/10_100m_ethernet-fifo_convertor/trunk/rtl/verilog/test_feedback.v
/10_100m_ethernet-fifo_convertor/trunk/rtl/verilog/TxModule.v