URL https://opencores.org/ocsvn/10_100m_ethernet-fifo_convertor/10_100m_ethernet-fifo_convertor/trunk

Subversion Repositories 10_100m_ethernet-fifo_convertor

[/] [10_100m_ethernet-fifo_convertor/] - Rev 9

Rev 9, 2009-12-06 14:03:52 GMT
Author: antiquity
Log message:
Implemented the RxModule with RAM instead of register, which greatly reduced the register consumptions; fixed the loose-frame bug of TxModule

Path
/10_100m_ethernet-fifo_convertor/trunk/rtl/verilog/common.v
/10_100m_ethernet-fifo_convertor/trunk/rtl/verilog/EthernetModule.v
/10_100m_ethernet-fifo_convertor/trunk/rtl/verilog/RxModule.v
/10_100m_ethernet-fifo_convertor/trunk/rtl/verilog/test_feedback.v
/10_100m_ethernet-fifo_convertor/trunk/rtl/verilog/TxModule.v