URL https://opencores.org/ocsvn/aes_highthroughput_lowarea/aes_highthroughput_lowarea/trunk

Subversion Repositories aes_highthroughput_lowarea

[/] [aes_highthroughput_lowarea/] [trunk/] - Rev 8

Rev 8, 2012-03-31 19:24:02 GMT
Author: motilito
Log message:
Added core specification document, core top example module and FPGA synthesis project files.

Path
/aes_highthroughput_lowarea/trunk/doc
/aes_highthroughput_lowarea/trunk/doc/HT LA AES Core Specifications.odt
/aes_highthroughput_lowarea/trunk/doc/HT LA AES Core Specifications.pdf
/aes_highthroughput_lowarea/trunk/verilog/bench/tb.v
/aes_highthroughput_lowarea/trunk/verilog/bench/tb_kat.v
/aes_highthroughput_lowarea/trunk/verilog/bench/test_imc.v
/aes_highthroughput_lowarea/trunk/verilog/rtl
/aes_highthroughput_lowarea/trunk/verilog/rtl/aes.v
/aes_highthroughput_lowarea/trunk/verilog/rtl/aes_top_example.v
/aes_highthroughput_lowarea/trunk/verilog/rtl/key_exp.v
/aes_highthroughput_lowarea/trunk/verilog/rtl/ram_16x64.v
/aes_highthroughput_lowarea/trunk/verilog/sim/icarus/test.log
/aes_highthroughput_lowarea/trunk/verilog/syn
/aes_highthroughput_lowarea/trunk/verilog/syn/altera
/aes_highthroughput_lowarea/trunk/verilog/syn/altera/aes_ht_la.qpf
/aes_highthroughput_lowarea/trunk/verilog/syn/altera/aes_ht_la.sdc
/aes_highthroughput_lowarea/trunk/verilog/syn/xilinx
/aes_highthroughput_lowarea/trunk/verilog/syn/xilinx/aes_ht_la.xise
/aes_highthroughput_lowarea/trunk/verilog/syn/xilinx/aes_top_example.ucf