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[/] [aes_highthroughput_lowarea/] [trunk/] [verilog/] [syn/] [xilinx/] - Rev 8

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Last modification

  • Rev 8, 2012-03-31 19:24:02 GMT
  • Author: motilito
  • Log message:
    Added core specification document, core top example module and FPGA synthesis project files.

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