URL https://opencores.org/ocsvn/cpu6502_true_cycle/cpu6502_true_cycle/trunk

Subversion Repositories cpu6502_true_cycle

[/] - Rev 14

Rev 14, 2009-01-09 20:45:15 GMT
Author: fpga_is_funny
Log message:
More optimizations...
- Second Phaze of removing unused nets & registers
- Added Verilog source on demand by some customers (for trial use)

Path
/trunk/rtl/verilog_TRIAL
/trunk/rtl/verilog_TRIAL/core.v
/trunk/rtl/verilog_TRIAL/fsm_execution_unit.v
/trunk/rtl/verilog_TRIAL/fsm_nmi.v
/trunk/rtl/verilog_TRIAL/r6502_tc.v
/trunk/rtl/verilog_TRIAL/regbank_axy.v
/trunk/rtl/verilog_TRIAL/reg_pc.v
/trunk/rtl/verilog_TRIAL/reg_sp.v
/trunk/rtl/vhdl/core.vhd
/trunk/rtl/vhdl/fsm_execution_unit.vhd
/trunk/rtl/vhdl/fsm_nmi.vhd
/trunk/rtl/vhdl/r6502_tc.vhd
/trunk/rtl/vhdl/R6502_TC_config.vhd
/trunk/rtl/vhdl/regbank_axy.vhd
/trunk/rtl/vhdl/reg_pc.vhd
/trunk/rtl/vhdl/reg_sp.vhd