URL https://opencores.org/ocsvn/cpu65c02_true_cycle/cpu65c02_true_cycle/trunk

Last modification

• Rev 13, 2009-02-25 18:50:17 GMT
• Author: fpga_is_funny

• Log message:

  - CORRECT "RTI" (wrong: use of stack pointer)
  - CORRECT "RMBx" & "SMBx" (wrong: bit translation)
  - RENAME all states of "FSM Execution Unit" for better reading
  - (85%) Finish working for Specification of cpu65C02_tc
  - CORRECT timing for addressing mode "ABS,X" for "INC" (wrong: 6 cycles instead of 7)
  - OPTIMIZE end states of "STA" (s197,s207,s200,s213)

Path
/trunk/rtl/Verilog
/trunk/rtl/Verilog/core.v
/trunk/rtl/Verilog/fsm_execution_unit.v
/trunk/rtl/Verilog/fsm_nmi.v
/trunk/rtl/Verilog/r65c02_tc.v
/trunk/rtl/Verilog/regbank_axy.v
/trunk/rtl/Verilog/reg_pc.v
/trunk/rtl/Verilog/reg_sp.v