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[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] - Rev 40

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Last modification

  • Rev 40, 2002-02-05 16:44:39 GMT
  • Author: mohor
  • Log message:
    Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
    MHz. Statuses, overrun, control frame transmission and reception still need
    to be fixed.

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