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[/] - Rev 15


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Last modification

  • Rev 15, 2001-08-06 14:44:29 GMT
  • Author: mohor
  • Log message:
    A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
    Include files fixed to contain no path.
    File names and module names changed ta have a eth_ prologue in the name.
    File eth_timescale.v is used to define timescale
    All pin names on the top module are changed to contain _I, _O or _OE at the end.
    Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
    and Mdo_OE. The bidirectional signal must be created on the top level. This
    is done due to the ASIC tools.

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