URL https://opencores.org/ocsvn/fade_ether_protocol/fade_ether_protocol/trunk

Last modification

• Rev 36, 2015-05-15 21:19:36 GMT
• Author: wzab

• Log message:

  Added signals needed to ensure, that Si570/1 chip generates the clock.
  Added signals driving the rate select lines in the SFP+ modules high.
  Added two XDC files - the first one for FM-S14 in the FMC1
  connector, the second one for FM-S14 in the FMC2 connector.

Path
/fade_ether_protocol/trunk/experimental_jumbo_frames_version/fpga/src/AFCK/AFCK_fade_top_4ch.vhd
/fade_ether_protocol/trunk/experimental_jumbo_frames_version/fpga/src/AFCK/fade_afck.xdc
/fade_ether_protocol/trunk/experimental_jumbo_frames_version/fpga/src/AFCK/fade_afck_fmc1.xdc
/fade_ether_protocol/trunk/experimental_jumbo_frames_version/fpga/src/AFCK/fade_afck_fmc2.xdc