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[/] - Rev 78


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Last modification

  • Rev 78, 2012-04-10 19:42:40 GMT
  • Author: ja_rd
  • Log message:
    Fixed a number of errors in the last refactor of the VHDL side of the project:
    - Path errors in the simulation scripts.
    - The reset pin in the C2SB mini-test-bench was not being driven.
    - The main vhdl test bench file was missing entirely.

    All of these errors due to not properly verifying the commit...

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