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[/] [minsoc/] [branches/] [rc-1.0/] [bench/] [verilog/] - Rev 59

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Last modification

  • Rev 59, 2011-04-28 21:59:30 GMT
  • Author: rfajardo
  • Log message:
    undefinition of NEGATIVE_RESET on minsoc_bench_defines.v cannot affect other inclusions of minsoc_defines.v. Instead, the testbench now works with the right reset level to avoid the implementation ordering problem.

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