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[/] [minsoc/] [branches/] [verilator/] [rtl/] [verilog/] - Rev 110


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Last modification

  • Rev 110, 2011-10-26 21:41:05 GMT
  • Author: rfajardo
  • Log message:
    Fixing several minor issues with the system:
    -minsoc-install splitted into installation and configuration can be used to configure a fresh checked out system
    -configure script used by both and to configure

    -rtl/verilog: svn externals fixed
    -or1200 rolled back to release-1.0

    -Makefile has been used by simulation to differentiate project definition of vhdl and verilog files
    -Altera was differentiating it in script
    -now there are two scripts, one for vhdl and another for verilog. The differentiation occurs in Makefile as for simulation.
    -altera_3c25_board/configure scripts had to be updated, vprj and vhdprj file extensions used to differentiate Verilog and VHDL project files.

    -prj/src: or1200_top.prj downdated to definition of or1200_v1

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