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[/] [minsoc/] [trunk/] [rtl/] [verilog/] - Rev 33

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  • Rev 33, 2010-10-07 13:19:10 GMT
  • Author: rfajardo
  • Log message:
    Start-up Starter, included in the MinSoC top file, has been updated to three-phase instruction output; instruction assertion, acknowledge assertion, and next instruction with acknowledge deassertion.

    Previously it was two-phase with next instruction, instruction assertion and acknowledge assertion together, and acknowledge deassertion.

    That is required by the new Wishbone master interface used by OpenRISC release 3.

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