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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] - Rev 63

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Last modification

  • Rev 63, 2013-02-26 14:45:30 GMT
  • Author: JonasDC
  • Log message:
    now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx

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