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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] - Rev 7

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Last modification

  • Rev 7, 2012-10-23 11:15:22 GMT
  • Author: JonasDC
  • Log message:
    Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
    added descriptive comments

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