URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] - Rev 63

Rev 63, 2013-02-26 14:45:30 GMT
Author: JonasDC
Log message:
now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx

Path
/mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_gen.vhd
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
/mod_sim_exp/trunk/rtl/vhdl/core/operand_mem_gen.vhd
/mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_gen.vhd