URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] - Rev 333

Rev 333, 2023-10-05 03:44:49 GMT
Author: jshamlet
Log message:
Fixed missing semicolons in o8_sys_timer_ii.vhd,
Added faulting address capture in the RAM models,
Modified o8_ram_1k.vhd to use 32-bit WPR

Path
/open8_urisc/trunk/VHDL/o8_ram_1k.vhd
/open8_urisc/trunk/VHDL/o8_ram_4k.vhd
/open8_urisc/trunk/VHDL/o8_sys_timer_ii.vhd