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[/] [open8_urisc/] [trunk/] [VHDL/] - Rev 224

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  • Rev 224, 2020-04-16 15:20:57 GMT
  • Author: jshamlet
  • Log message:
    Finished new Open8 bus record, which now includes the clock, reset and a microsecond tick. The CPU now accepts a clock and pll_locked signal, which it uses to generate the system reset in the bus record. It also contains a simple microsecond counter to feed the usec_tick in the record. This logic was removed from the real time clock and system timer entities, which now use the global version. Bus connections should be dramatically simplified, as only the read logic and interrupts are still run as separate signals.

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