URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] - Rev 209

Rev 209, 2020-04-09 01:40:42 GMT
Author: jshamlet
Log message:
Fixed an issue in the PIT timer that caused an immediate interrupt on interval write,
Fixed an issue in the epoch timer that resulted in a spurious interrupt due to extra LSB's being set by default in the set point register,
While cleaning elsewhere, founding a spacing issue in the CPU HDL,
Added a 4k ROM and MW core.

Path
/open8_urisc/trunk/VHDL/async_ser_rx.vhd
/open8_urisc/trunk/VHDL/async_ser_tx.vhd
/open8_urisc/trunk/VHDL/o8_async_serial.vhd
/open8_urisc/trunk/VHDL/o8_cpu.vhd
/open8_urisc/trunk/VHDL/o8_epoch_timer.vhd
/open8_urisc/trunk/VHDL/o8_ram_4k.vhd
/open8_urisc/trunk/VHDL/o8_rtc.vhd
/open8_urisc/trunk/VHDL/ram_4k_core.vhd