URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [bench/] - Rev 72

Rev 72, 2010-08-01 18:54:37 GMT
Author: olivier.girard
Log message:
Expand configurability options of the program and data memory sizes.

Path
/openmsp430/trunk/core/bench/verilog/ram.v
/openmsp430/trunk/core/bench/verilog/tb_openMSP430.v
/openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v
/openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v
/openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim
/openmsp430/trunk/doc/html/core.html
/openmsp430/trunk/doc/html/overview.html
/openmsp430/trunk/doc/html/software_development_tools.html
/openmsp430/trunk/doc/openMSP430.odt
/openmsp430/trunk/doc/openMSP430.pdf
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430_defines.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430_undefines.v
/openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/bin/msp430sim
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_defines.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_undefines.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/bin/msp430sim