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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] - Rev 81

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Last modification

  • Rev 81, 2010-12-05 21:45:34 GMT
  • Author: olivier.girard
  • Log message:
    Initial synthesis, P&R setup for the Actel example project.

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