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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] - Rev 157

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Last modification

  • Rev 157, 2012-10-15 21:44:57 GMT
  • Author: olivier.girard
  • Log message:
    Re-create new LX9 Microboard project to show off the new I2C serial debug interface (and more to come)....
Path
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/bench
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/bench/verilog
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/bench/verilog/glbl.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/bench/verilog/msp_debug.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/bench/verilog/ram.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/bench/verilog/ram_16x2k.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/bench/verilog/ram_16x512.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/bench/verilog/registers.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/bench/verilog/tb_openMSP430_fpga.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/bench/verilog/timescale.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/doc
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/doc/Avt_S6LX9_MicroBoard_UCF_110804.ucf
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/doc/Spartan-6_LX9_RevB1_Schematic.pdf
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/doc/Spartan-6_SelectIO_Resources_ug381.pdf
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/doc/U75_Avnet_Spartan-6_LX9_MicroBoard_Configuration_Guide_v13_2_1.pdf
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/doc/Xilinx_Spartan-6_LX9_MicroBoard_Rev_B2_Hardware_User_Guide.pdf
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/coregen.cgc
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/coregen.cgp
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/coregen.log
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k.asy
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/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/blk_mem_gen_v7_2_readme.txt
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/doc
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/doc/blk_mem_gen_v7_2_vinfo.html
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/doc/pg058-blk-mem-gen.pdf
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/example_design
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/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/example_design/ram_16x2k_prod.vhd
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/implement
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/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/implement/planAhead_ise.sh
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/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/simulation
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/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/simulation/functional/simulate_isim.sh
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/simulation/functional/simulate_mti.bat
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/simulation/functional/simulate_mti.do
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/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/simulation/functional/simulate_vcs.sh
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/simulation/functional/ucli_commands.key
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