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Subversion Repositories openmsp430

[/] - Rev 202

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Last modification

  • Rev 202, 2015-07-01 21:13:32 GMT
  • Author: olivier.girard
  • Log message:
    Add DMA interface support + LINT cleanup
Path
/openmsp430/trunk/core/bench/verilog/dma_tasks.v
/openmsp430/trunk/core/bench/verilog/tb_openMSP430.v
/openmsp430/trunk/core/rtl/verilog/filelist.f
/openmsp430/trunk/core/rtl/verilog/omsp_alu.v
/openmsp430/trunk/core/rtl/verilog/omsp_and_gate.v
/openmsp430/trunk/core/rtl/verilog/omsp_clock_gate.v
/openmsp430/trunk/core/rtl/verilog/omsp_clock_module.v
/openmsp430/trunk/core/rtl/verilog/omsp_clock_mux.v
/openmsp430/trunk/core/rtl/verilog/omsp_dbg.v
/openmsp430/trunk/core/rtl/verilog/omsp_dbg_hwbrk.v
/openmsp430/trunk/core/rtl/verilog/omsp_dbg_i2c.v
/openmsp430/trunk/core/rtl/verilog/omsp_dbg_uart.v
/openmsp430/trunk/core/rtl/verilog/omsp_execution_unit.v
/openmsp430/trunk/core/rtl/verilog/omsp_frontend.v
/openmsp430/trunk/core/rtl/verilog/omsp_mem_backbone.v
/openmsp430/trunk/core/rtl/verilog/omsp_multiplier.v
/openmsp430/trunk/core/rtl/verilog/omsp_register_file.v
/openmsp430/trunk/core/rtl/verilog/omsp_scan_mux.v
/openmsp430/trunk/core/rtl/verilog/omsp_sfr.v
/openmsp430/trunk/core/rtl/verilog/omsp_sync_cell.v
/openmsp430/trunk/core/rtl/verilog/omsp_sync_reset.v
/openmsp430/trunk/core/rtl/verilog/omsp_wakeup_cell.v
/openmsp430/trunk/core/rtl/verilog/omsp_watchdog.v
/openmsp430/trunk/core/rtl/verilog/openMSP430.v
/openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v
/openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v
/openmsp430/trunk/core/sim/rtl_sim/bin/asm2ihex.sh
/openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim
/openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim_c
/openmsp430/trunk/core/sim/rtl_sim/bin/parse_results
/openmsp430/trunk/core/sim/rtl_sim/bin/parse_summaries
/openmsp430/trunk/core/sim/rtl_sim/bin/rtlsim.sh
/openmsp430/trunk/core/sim/rtl_sim/bin/template_defs.asm
/openmsp430/trunk/core/sim/rtl_sim/run/run
/openmsp430/trunk/core/sim/rtl_sim/run/run_all
/openmsp430/trunk/core/sim/rtl_sim/run/run_all_mpy
/openmsp430/trunk/core/sim/rtl_sim/run/run_c
/openmsp430/trunk/core/sim/rtl_sim/run/run_disassemble
/openmsp430/trunk/core/sim/rtl_sim/run/simvision.svcf
/openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/coremark_v1.0.v
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/dhrystone_4mcu.v
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/dhrystone_v2.1.v
/openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/sandbox.v
/openmsp430/trunk/core/sim/rtl_sim/src/clock_module.v
/openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic.v
/openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_lfxt.v
/openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_mclk.v
/openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_smclk.v
/openmsp430/trunk/core/sim/rtl_sim/src/core.f
/openmsp430/trunk/core/sim/rtl_sim/src/cpu_startup_asic.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_cpu.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_halt_irq.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk0.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk1.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk2.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk3.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_mem.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_onoff.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_onoff_asic.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_rdwr.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_sync.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_cpu.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_halt_irq.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk0.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk1.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk2.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk3.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_mem.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_onoff.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_onoff_asic.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_rdwr.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_sync.v
/openmsp430/trunk/core/sim/rtl_sim/src/dma_dbg_arbiter.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dma_dbg_arbiter.v
/openmsp430/trunk/core/sim/rtl_sim/src/dma_lpm0_asic.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dma_lpm0_asic.v
/openmsp430/trunk/core/sim/rtl_sim/src/dma_lpm1_asic.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dma_lpm1_asic.v
/openmsp430/trunk/core/sim/rtl_sim/src/dma_lpm2_asic.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dma_lpm2_asic.v
/openmsp430/trunk/core/sim/rtl_sim/src/dma_lpm3_asic.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dma_lpm3_asic.v
/openmsp430/trunk/core/sim/rtl_sim/src/dma_lpm4_asic.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dma_lpm4_asic.v
/openmsp430/trunk/core/sim/rtl_sim/src/dma_rdwr_8b.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dma_rdwr_8b.v
/openmsp430/trunk/core/sim/rtl_sim/src/dma_rdwr_16b.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dma_rdwr_16b.v
/openmsp430/trunk/core/sim/rtl_sim/src/dma_resp.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dma_resp.v
/openmsp430/trunk/core/sim/rtl_sim/src/irq32.v
/openmsp430/trunk/core/sim/rtl_sim/src/irq64.v
/openmsp430/trunk/core/sim/rtl_sim/src/lp_modes_asic.v
/openmsp430/trunk/core/sim/rtl_sim/src/lp_modes_dbg_asic.v
/openmsp430/trunk/core/sim/rtl_sim/src/mpy_basic.v
/openmsp430/trunk/core/sim/rtl_sim/src/mpy_mac.v
/openmsp430/trunk/core/sim/rtl_sim/src/mpy_macs.v
/openmsp430/trunk/core/sim/rtl_sim/src/mpy_mpy.v
/openmsp430/trunk/core/sim/rtl_sim/src/mpy_mpys.v
/openmsp430/trunk/core/sim/rtl_sim/src/nmi.v
/openmsp430/trunk/core/sim/rtl_sim/src/op_modes.s43
/openmsp430/trunk/core/sim/rtl_sim/src/op_modes.v
/openmsp430/trunk/core/sim/rtl_sim/src/op_modes_asic.v
/openmsp430/trunk/core/sim/rtl_sim/src/sandbox.s43
/openmsp430/trunk/core/sim/rtl_sim/src/sandbox.v
/openmsp430/trunk/core/sim/rtl_sim/src/scan.v
/openmsp430/trunk/core/sim/rtl_sim/src/submit.f
/openmsp430/trunk/core/sim/rtl_sim/src/tA_capture.v
/openmsp430/trunk/core/sim/rtl_sim/src/tA_clkmux.v
/openmsp430/trunk/core/sim/rtl_sim/src/tA_compare.v
/openmsp430/trunk/core/sim/rtl_sim/src/tA_modes.v
/openmsp430/trunk/core/sim/rtl_sim/src/tA_output.v
/openmsp430/trunk/core/sim/rtl_sim/src/wdt_clkmux.v
/openmsp430/trunk/core/sim/rtl_sim/src/wdt_interval.v
/openmsp430/trunk/core/sim/rtl_sim/src/wdt_watchdog.v
/openmsp430/trunk/core/sim/rtl_sim/src/wdt_wkup.v
/openmsp430/trunk/doc/html/core.html
/openmsp430/trunk/doc/html/dma_interface.html
/openmsp430/trunk/doc/html/images/core_integration.odg
/openmsp430/trunk/doc/html/images/core_integration.png
/openmsp430/trunk/doc/html/images/cpu_structure.odg
/openmsp430/trunk/doc/html/images/cpu_structure.png
/openmsp430/trunk/doc/html/images/dma_bootloader.png
/openmsp430/trunk/doc/html/images/dma_clock_domains.png
/openmsp430/trunk/doc/html/images/dma_interface.odg
/openmsp430/trunk/doc/html/images/dma_interface_complex_sys.png
/openmsp430/trunk/doc/html/images/dma_interface_simple_sys.png
/openmsp430/trunk/doc/html/images/dma_waveforms.odg
/openmsp430/trunk/doc/html/images/dma_waveform_bootloader.png
/openmsp430/trunk/doc/html/images/dma_waveform_error_resp.png
/openmsp430/trunk/doc/html/images/dma_waveform_multiple.png
/openmsp430/trunk/doc/html/images/dma_waveform_priority.png
/openmsp430/trunk/doc/html/images/dma_waveform_simple.png
/openmsp430/trunk/doc/html/images/dma_waveform_wait_states.png
/openmsp430/trunk/doc/html/images/wave_dma.odg
/openmsp430/trunk/doc/html/images/wave_dma.png
/openmsp430/trunk/doc/html/integration.html
/openmsp430/trunk/doc/html/overview.html
/openmsp430/trunk/doc/html/peripherals.html
/openmsp430/trunk/doc/html/serial_debug_interface.html
/openmsp430/trunk/doc/openMSP430.odt
/openmsp430/trunk/doc/openMSP430.pdf
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/filelist.f
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_alu.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_and_gate.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_clock_gate.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_clock_module.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_clock_mux.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg_hwbrk.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg_i2c.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg_uart.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_execution_unit.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_frontend.v
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/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_sync_cell.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_sync_reset.v
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/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_watchdog.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430.v
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/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openMSP430_fpga.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/software/spacewar/linker.x
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/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_and_gate.v
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/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_sync_reset.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_wakeup_cell.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_watchdog.v
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/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/omsp_uart.v
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/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_clock_gate.v
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/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_sync_reset.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_wakeup_cell.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_watchdog.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_defines.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_undefines.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openMSP430_fpga.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/submit.f
/openmsp430/trunk/fpga/xilinx_diligent_s3board/software/hw_uart/linker.x
/openmsp430/trunk/fpga/xilinx_diligent_s3board/software/leds/linker.x

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