OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] - Rev 815

Rev

Directory listing | View Log | Compare with Previous | RSS feed

Last modification

  • Rev 815, 2012-10-04 09:52:36 GMT
  • Author: yannv
  • Log message:
    OR1200 debug unit: prevent deadlock when trap instruction stalls

    As per mailing list post <20120925160925.5725e06f@latmask.vernier.se>,
    the debug unit could deadlock with the instruction decoder if the trap
    instruction is held back by a pipeline stall. This change prevents that.

    The problem can be reproduced by placing a breakpoint at an unfavorable
    position with instruction cache enabled. In our test, this occurred
    with or1200-cbasic when placing a breakpoint at test_bss using gdb, but
    this is dependent on such factors as cache parameters and compilation
    result.

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.