OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] - Rev 530

Rev

Directory listing | View Log | Compare with Previous | RSS feed

Last modification

  • Rev 530, 2011-04-26 09:32:10 GMT
  • Author: julius
  • Log message:
    ORPSoC update

    Ethernet MAC Wishbone interface fixes

    Beginnings of software update.

    ML501 backend script fixes for new ISE
Path
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/bench/verilog/include/eth_stim.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/or1200_defines.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/syn/synplify/bin/Makefile
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/bin/Makefile
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/include/eth_stim.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/ethmac_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/orpsoc-defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/orpsoc_top/orpsoc_top.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/xst/bin/Makefile
/openrisc/trunk/orpsocv2/doc/orpsoc.texi
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_fifo.v
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_wishbone.v
/openrisc/trunk/orpsocv2/sim/bin/Makefile
/openrisc/trunk/orpsocv2/sw/drivers/ethmac/include/ethmac.h
/openrisc/trunk/orpsocv2/sw/drivers/or1200/cache.S
/openrisc/trunk/orpsocv2/sw/drivers/or1200/crt0.S
/openrisc/trunk/orpsocv2/sw/drivers/or1200/int.c
/openrisc/trunk/orpsocv2/sw/drivers/or1200/link.ld
/openrisc/trunk/orpsocv2/sw/drivers/or1200/Makefile
/openrisc/trunk/orpsocv2/sw/Makefile.inc
/openrisc/trunk/orpsocv2/sw/tests/ethmac/board/ethmac-ping.c
/openrisc/trunk/orpsocv2/sw/tests/ethmac/sim/ethmac-rxtxcallresponse.c
/openrisc/trunk/orpsocv2/sw/tests/ethmac/sim/ethmac-rxtxoverflow.c
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-basic.S
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-cy.S
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-except.S
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-intsyscall.S

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.