URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Last modification

• Rev 364, 2010-09-12 17:48:45 GMT
• Author: julius

• Log message:

  OR1200 passes verilator lint. Mainly fixes to widths, and all case statements
  altered to casez and Xs changed to ?s.
  
  OR1200 PIC default width back to 31 (was accidentally changed to ORPSoC's 20
  last checkin)
  
  OR1200 spec updated to version 0.9, various updates.
  
  OR1200 in ORPSoC and main OR1200 in sync, only difference is defines.

Path
/openrisc/trunk/or1200/doc/openrisc1200_spec.doc
/openrisc/trunk/or1200/doc/openrisc1200_spec.odt
/openrisc/trunk/or1200/doc/openrisc1200_spec.pdf
/openrisc/trunk/or1200/rtl/verilog/or1200_alu.v
/openrisc/trunk/or1200/rtl/verilog/or1200_ctrl.v
/openrisc/trunk/or1200/rtl/verilog/or1200_dc_fsm.v
/openrisc/trunk/or1200/rtl/verilog/or1200_defines.v
/openrisc/trunk/or1200/rtl/verilog/or1200_dmmu_top.v
/openrisc/trunk/or1200/rtl/verilog/or1200_du.v
/openrisc/trunk/or1200/rtl/verilog/or1200_except.v
/openrisc/trunk/or1200/rtl/verilog/or1200_fpu.v
/openrisc/trunk/or1200/rtl/verilog/or1200_fpu_arith.v
/openrisc/trunk/or1200/rtl/verilog/or1200_fpu_fcmp.v
/openrisc/trunk/or1200/rtl/verilog/or1200_fpu_post_norm_addsub.v
/openrisc/trunk/or1200/rtl/verilog/or1200_fpu_post_norm_div.v
/openrisc/trunk/or1200/rtl/verilog/or1200_fpu_post_norm_intfloat_conv.v
/openrisc/trunk/or1200/rtl/verilog/or1200_fpu_post_norm_mul.v
/openrisc/trunk/or1200/rtl/verilog/or1200_fpu_pre_norm_addsub.v
/openrisc/trunk/or1200/rtl/verilog/or1200_fpu_pre_norm_div.v
/openrisc/trunk/or1200/rtl/verilog/or1200_freeze.v
/openrisc/trunk/or1200/rtl/verilog/or1200_genpc.v
/openrisc/trunk/or1200/rtl/verilog/or1200_gmultp2_32x32.v
/openrisc/trunk/or1200/rtl/verilog/or1200_lsu.v
/openrisc/trunk/or1200/rtl/verilog/or1200_mult_mac.v
/openrisc/trunk/or1200/rtl/verilog/or1200_operandmuxes.v
/openrisc/trunk/or1200/rtl/verilog/or1200_reg2mem.v
/openrisc/trunk/or1200/rtl/verilog/or1200_sprs.v
/openrisc/trunk/or1200/rtl/verilog/or1200_top.v
/openrisc/trunk/or1200/rtl/verilog/or1200_wbmux.v
/openrisc/trunk/or1200/rtl/verilog/or1200_wb_biu.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_fpu.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_fpu_arith.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_fpu_fcmp.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_fpu_post_norm_addsub.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_fpu_post_norm_div.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_fpu_post_norm_intfloat_conv.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_fpu_post_norm_mul.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_fpu_pre_norm_addsub.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_fpu_pre_norm_div.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_gmultp2_32x32.v
/openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_defines.v