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Last modification

  • Rev 568, 2011-07-02 10:28:18 GMT
  • Author: julius
  • Log message:
    OPRSoC - adding Xilinx Xtreme DSP Spartan-3A 1800A board port and documentation
Path
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/backend
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/backend/bin
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/backend/bin/s3adsp_ddr2_cache.ngc
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/backend/par
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/backend/par/bin
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/backend/par/bin/Makefile
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/backend/par/bin/s3adsp1800.ucf
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/backend/par/prebuilt
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/backend/par/run
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/backend/par/run/Makefile
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/bench
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/bench/verilog
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/bench/verilog/ddr2_model.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/bench/verilog/include
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/bench/verilog/include/ddr2_model_parameters.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/bench/verilog/include/ddr2_model_preload.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/bench/verilog/include/eth_phy_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/bench/verilog/include/eth_stim.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/bench/verilog/include/synthesis-defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/bench/verilog/include/timescale.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/bench/verilog/orpsoc_testbench.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/Makefile.inc
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/modules
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/README
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/arbiter
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/arbiter/arbiter_bytebus.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/arbiter/arbiter_dbus.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/arbiter/arbiter_ibus.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/clkgen
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/clkgen/clkgen.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/gpio
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/gpio/gpio.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/gpio/README
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/include
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/include/dbg_cpu_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/include/dbg_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/include/dbg_wb_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/include/ethmac_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/include/i2c_master_slave_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/include/or1200_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/include/orpsoc-defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/include/orpsoc-params.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/include/s3adsp_ddr2_parameters_0.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/include/tap_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/include/uart_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/orpsoc_top
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/orpsoc_top/orpsoc_top.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_cache.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_cal_ctl.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_cal_top.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_clk_dcm.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_controller_0.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_controller_iobs_0.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_data_path_0.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_data_path_iobs_0.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_data_read_0.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_data_read_controller_0.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_data_write_0.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_dqs_delay.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_fifo_0_wr_en_0.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_fifo_1_wr_en_0.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_infrastructure.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_infrastructure_iobs_0.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_infrastructure_top.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_iobs_0.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_ram8d_0.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_rd_gray_cntr.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_s3_dm_iob.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_s3_dqs_iob.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_s3_dq_iob.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_tap_dly.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_top_0.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_wr_gray_cntr.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/xilinx_s3adsp_ddr2.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/xilinx_s3adsp_ddr2_if.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sim
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sim/bin
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sim/bin/Makefile
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sim/out
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sim/run
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sim/run/Makefile
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/board
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/board/include
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/board/include/board.h
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/bootrom
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/bootrom/bootrom.v
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/bootrom/Makefile
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/Makefile.inc
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/tests
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/tests/ddr2cache
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/tests/ddr2cache/sim
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/tests/ddr2cache/sim/ddr2cache-1.S
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/tests/ddr2cache/sim/ddr2cache-2.S
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/tests/ddr2cache/sim/Makefile
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/tests/ethmac
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/tests/ethmac/sim
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/tests/ethmac/sim/ethmac-rx.c
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/tests/ethmac/sim/ethmac-rxtx.c
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/tests/ethmac/sim/ethmac-rxtxcallresponse.c
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/tests/ethmac/sim/ethmac-tx.c
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/tests/ethmac/sim/Makefile
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/syn
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/syn/xst
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/syn/xst/bin
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/syn/xst/bin/Makefile
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/syn/xst/out
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/syn/xst/run
/openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/syn/xst/run/Makefile
/openrisc/trunk/orpsocv2/doc/orpsoc.texi

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