URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] - Rev 351

Rev 351, 2010-09-07 17:46:42 GMT
Author: julius
Log message:
OR1200 with icarus fixed up. MMu test fix, remove testfloat elf, adding new arbiter and RAM, may break verilator compatibility... TODO

Path
/openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_dc_top.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/wb_ram_b3
/openrisc/trunk/orpsocv2/rtl/verilog/components/wb_ram_b3/wb_ram_b3.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/wb_switch_b3
/openrisc/trunk/orpsocv2/rtl/verilog/components/wb_switch_b3/wb_switch_b3.v
/openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top.v
/openrisc/trunk/orpsocv2/sim/bin/icarus.scr
/openrisc/trunk/orpsocv2/sim/bin/Makefile
/openrisc/trunk/orpsocv2/sim/bin/modelsim.scr
/openrisc/trunk/orpsocv2/sim/bin/verilator.scr
/openrisc/trunk/orpsocv2/sw/include/spr-defs.h
/openrisc/trunk/orpsocv2/sw/or1200/or1200-mmu.c
/openrisc/trunk/orpsocv2/sw/testfloat/testfloat.elf