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[/] - Rev 81

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Last modification

Rev 81, 2003-01-30 22:01:36 GMT
Author: mihad
Log message:
Updated synchronization in top level fifo modules.

Path
/trunk/bench/verilog/system.v
/trunk/rtl/verilog/pci_pciw_pcir_fifos.v
/trunk/rtl/verilog/pci_wbw_wbr_fifos.v
/trunk/rtl/verilog/pci_wb_master.v
/trunk/sim/rtl_sim/run/run_pci_sim_regr.scr

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